1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor memory having a latch circuit using a ferroelectric capacitor.
2. Description of the Related Art
In general, a latch circuit formed in a semiconductor integrated circuit is volatile, and therefore, data which is held therein is lost after turning-off of the power. Recently, a latch circuit is formed by using a ferroelectric film as a variable capacitor, and a nonvolatile SRAM (Static Random Access Memory) which adopts this latch circuit as a memory cell has been proposed (T. Miwa et al. in Proc. of CICC, May 2000, pp65-68).
FIG. 1 shows a memory cell of a semiconductor memory of this kind.
The memory cell includes a latch circuit 2 which is composed of two CMOS inverters 1a and 1b whose inputs and outputs are connected to each other, ferroelectric capacitors 3a and 3b which are respectively connected to input nodes N and NX of the CMOS inverters 1a and 1b, and transfer transistors 4a and 4b which connect the input nodes N and NX to bit lines BL and BLX, respectively. Gates of the transfer transistors 4a and 4b are connected to a word line WL.
In this memory cell, data which is written into the latch circuit 2 is held as residual dielectric polarization of the ferroelectric capacitors 3a and 3b after turning the power off.
When turning the power on, input voltages of the CMOS inverters 1a and 1b are unbalanced due to a capacitance difference between the nodes N and NX, which corresponds to the residual dielectric polarization. Namely, the data held therein before turning-off of the power is written in the latch circuit 2 again by using the residual dielectric polarization of the ferroelectric capacitors 3a and 3b. This operation is referred to as recall operation.
Hereinafter, an explanation about turning the power on will be given in detail. First, a plate voltage PL of the ferroelectric capacitors 3a and 3b is fixed to a ground voltage VSS (0 V), and a power source voltage VDD and the ground voltage VSS are supplied to the CMOS inverters 1a and 1b which compose the latch circuit 2. Capacitance values of the ferroelectric capacitors 3a and 3b are different corresponding to polarized states.
The ferroelectric capacitor 3a with a large capacitance value takes much time to increase a voltage, as compared with the ferroelectric capacitor 3b with a small capacitance value. Hence, a minute voltage difference is generated between the nodes N and NX. This voltage difference is amplified by a differential amplification operation of the latch circuit 2, together with the supply of power source. Then, the nodes N and NX are finally fixed to the power source voltage VDD or the ground voltage VSS. Namely, the data before turning-off of the power is reproduced.
When the power source voltage VDD rises in turning the power on, the nodes N and NX of the latch circuit 2 are respectively charged from a power source line VDD through pMOS transistors of the CMOS inverters 1a and 1b. Meanwhile, electrical charges of the nodes N and NX are respectively discharged to a ground line VSS through nMOS transistors of the CMOS inverters 1a and 1b. 
When the power source voltage VDD is low, voltages of the nodes N and NX are determined by leak currents of the pMOS transistors and nMOS transistors and capacitances of the nodes N and NX. For example, it is supposed that threshold voltages of the pMOS transistors of the CMOS inverters 1a and 1b vary by xcex94Vth=80 mV. At this time, leak currents of the pMOS transistors differ by an order of magnitude (supposing that an S factor=80 mV). Supposing that threshold voltages of the nMOS transistors of the CMOS inverters 1a and 1b are the same, charging currents of the nodes N and NX become the ones corresponding to the leak currents of the pMOS transistors, respectively.
Real currents for charging the capacitances of the nodes N and NX (including the ferroelectric capacitors 3a and 3b which are respectively connected to the nodes N and NX) are supposed to be In=1 nA and Inx=0.1 nA, respectively. It should be mentioned that the real currents are differences between the leak currents of the pMOS transistors and the leak currents of the nMOS transistors in the CMOS inverters 1a and 1b. Further, the capacitances of the nodes N and NX (including the ferroelectric capacitors 3a and 3b) are supposed to be Cn=200 fF and Cnx=50 fF, respectively.
In this case, voltages Vn and Vnx of the nodes N and NX after 0.5 ms from the turning-on of the power can be expressed by the following expressions (1) and (2).
Vn=Qn/Cn=(Inxc3x970.5Exe2x88x923)/Cn=0.25[V]xe2x80x83xe2x80x83(1) 
Vnx=Qnx/Cnx=(Inxxc3x970.5Exe2x88x923)/Cnx=0.1[V]xe2x80x83xe2x80x83(2) 
Actually, the difference between the voltages Vn and Vnx increases further because the latch circuit 2 has an amplifying function. In the above example, due to the rise of the power source voltage, the node N finally becomes the power source voltage VDD (logic xe2x80x9cHxe2x80x9d) and the node NX becomes the ground voltage VSS (logic xe2x80x9cLxe2x80x9d).
However, the node N, which originally has a large parasitic capacitance, requires a long charging time, and its logic should be the logic xe2x80x9cLxe2x80x9d. The node NX, which has a small parasitic capacitance, requires a short charging time, and its logic should be the logic xe2x80x9cHxe2x80x9d.
Namely, according to the memory cell shown in FIG. 1, wrong data is reproduced due to variations of the threshold voltages of the pMOS transistors.
Incidentally, wrong recall operation is also caused by variations of the threshold voltages of the nMOS transistors. This kind of malfunction occurs not only in the memory cell, but also in a latch circuit using the residual dielectric polarization of the ferroelectric capacitors.
It is an object of the present invention to surely perform recall operation of a memory cell and of a latch circuit which use residual dielectric polarization of ferroelectric capacitors.
According to one of the aspects of the present invention, inputs and outputs of two buffer circuits are connected to each other to form a latch circuit. One ends of a pair of ferroelectric capacitors are respectively connected to inputs of the buffer circuits. The other ends of the ferroelectric capacitors are connected to a first plate line. Data held in the latch circuit before turning-off of the power is held as residual dielectric polarization of the ferroelectric capacitors. The latch circuit and the ferroelectric capacitors of the present invention are applied to, for example, at least one of a master latch circuit and a slave latch circuit which are connected in cascade in a storage circuit, or to a memory cell of a semiconductor memory.
A first plate voltage generator generates a first plate voltage to be supplied to the first plate line. After the power turns on, voltages of the other ends of the ferroelectric capacitors rise as the first plate voltage rises. Voltages of the one ends of the ferroelectric capacitors rise according to capacitance values corresponding to polarization of the ferroelectric capacitors, due to a capacitance coupling effect of the ferroelectric capacitors. Namely, before power source is supplied to the two buffer circuits, the input voltages of the buffer circuits become different from each other.
A switch control circuit activates a switch control signal when the first plate voltage rises to a predetermined voltage after the power turns on. A switch circuit turns on in response to the activation of the switch control signal, and connects power supply terminals of the buffer circuits to a power source line. At this time, the input voltages of the buffer circuits are different from each other, and therefore, logic data is written into the latch circuit according to each of the input voltages. As a result of this, data held in the latch circuit before turning-off of the power can be reproduced. Namely, normal recall operation is performed.
According to another aspect of the present invention, a latch circuit is formed of two buffer circuits whose inputs and outputs are connected to each other. A pair of first ferroelectric capacitors are connected in series between a first plate line and a second plate line. An intermediate node which connects the two first ferroelectric capacitors is connected to an input of one of the buffer circuits. A pair of second ferroelectric capacitors are connected in series between the first plate line and the second plate line. An intermediate node which connects the two second ferroelectric capacitors is connected to an input of the other of the buffer circuits. Data held in the latch circuit before turning-off of the power is held as residual dielectric polarization of the ferroelectric capacitors. The latch circuit and the ferroelectric capacitors of the present invention are applied to, for example, at least one of a master latch circuit and a slave latch circuit which are connected in cascade in a storage circuit, or to a memory cell of a semiconductor memory.
A first plate voltage generator generates a first plate voltage to be supplied to the first plate line. A second plate voltage generator generates a second plate voltage which is supplied to the second plate line for a predetermined period after the power turns on. During this period, the second plate voltage is lower than the first plate voltage and is fixed to, for example, a ground voltage. After the power turns on, voltages of the respective intermediate nodes of the first ferroelectric capacitors and of the second ferroelectric capacitors rise according to capacitance division of these ferroelectric capacitors, as the first plate voltage rises. Namely, before power source is supplied to the two buffer circuits, the input voltages of the buffer circuits become different from each other.
A switch control circuit activates a switch control signal when the first plate voltage rises to a predetermined voltage after the power turns on. A switch circuit turns on in response to the activation of the switch control signal, and connects power supply terminals of the buffer circuits to a power source line. At this time, the input voltages of the buffer circuits are different from each other, and therefore, logic data is written into the latch circuit according to each of the input voltages. As a result of this, data held in the latch circuit before turning-off of the power can be reproduced. Namely, normal recall operation is performed.
According to another aspect of the present invention, each of buffer circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor. A source of the pMOS transistor is connected to a power source line through a switch circuit, and a substrate of the pMOS transistor is connected to the power source line. A source of the nMOS transistor is connected to a ground line through a switch circuit, and a substrate of the nMOS transistor is connected to the ground line. Therefore, it is possible to prevent floating of the substrates at the time of turning-on of the power, and to prevent a malfunction of the transistors (latchup or the like).
According to another aspect of the present invention, a switch circuit is formed to be common to a plurality of memory cells. This reduces a total number of the switch circuits, thereby reducing a chip size of a semiconductor memory.